Join to apply for the Packet Processor Architect role at Eridu AI 2 weeks ago Be among the first 25 applicants Join to apply for the Packet Processor Architect role at Eridu AI Direct message the job poster from Eridu AI Chico & San Francisco Bay Area, CA -- Innovative global talent acquisition leader with proven expertise in implementing scalable recruiting solutions Eridu AI is a Silicon Valley hardware startup focused on accelerating training and inference performance for large AI models. Today’s AI model performance is often gated by infrastructure bottlenecks. Eridu AI introduces multiple industry-first innovations across semiconductors, software and systems to deliver solutions that improves AI data center performance to increase GPU utilization while simultaneously reducing capex and power. Eridu AI’s solution and value proposition have been widely validated with several hyperscalers. The company is led by a veteran team of Silicon Valley executives and engineers with decades of experience in state-of-the-art semiconductors, optics, software, and systems, including serial entrepreneur Drew Perkins, co-founder of Infinera (NASDAQ: INFN), Lightera (acq. by Ciena), Gainspeed (acq. by Nokia) and Mojo Vision (World’s leading micro-LED display company and developer of the first augmented reality contact lens). Position Overview We are looking for a highly experienced Packet Processor Architect to lead the definition and implementation of Eridu's industry leading Networking ASIC. This is a unique opportunity to help shape the future of AI Networking. Responsibilities Define and architect packet processing pipelines including related lookup tables and metadata structures for high-performance networking ASICs, including ingress/egress processing, switching/bridging and routing, hash tables and memory lookups, classification, ACL, various tunneling protocols like VxLAN, GRE, IPinIP, QoS, scheduling, traffic management, and congestion control. Work closely with the CTO to translate high-level system requirements and customer use cases into detailed architecture and functional specifications. Collaborate with the chip and system microarchitects to align the packet processor architecture with system-level goals for throughput, latency, programmability, and power efficiency. Lead modeling and feasibility analysis of packet flow behavior across L2/L3/L4 layers to validate architectural choices, including throughput, latency, power and area efficiencies. Drive architectural decisions involving classification, table and lookup optimizations, resource allocation and scalability. Work closely with RTL, Verification, Firmware, and Physical Design teams to ensure seamless design implementation and handoff. Guide integration of internal and external IPs (e.g., TCAM, MAC, PCIe, SerDes, DMA) into the broader packet architecture. Participate in design reviews, performance modeling, Test and Verification strategies and architectural trade-off analysis. Provide support for various networking protocols and standards related to packet processing Contribute to post-silicon validation and tuning of packet flows for performance and correctness. Investigate and resolve complex issues related to packet processing, working closely with cross-functional teams including hardware engineers, firmware developers, and system architects. Define architecture-level development methodologies and influence cross-functional design best practices. Required Qualifications MSEE or equivalent with 15+ years of experience in networking or data-path ASIC architecture and design. Proven success in architecting packet-processing engines in high-throughput ASICs or SoCs. Experience in designing hash functions, hash tables and lookup engine optimizations. Deep understanding of networking protocols (Ethernet, TCP/IP, UDP, VLAN, MPLS, RoCE, etc.) and their hardware implications. Familiarity with programmable pipelines, parser/deparser logic, and hardware scheduling engines. Demonstrated expertise in microarchitecture definition, performance modeling, and trade-off analysis. Solid experience working across the ASIC development lifecycle, from concept through productization. Experience in high-speed I/O integration (e.g., PCIe Gen5/Gen6, UCIe, SerDes, DMA engines) is a plus. Understanding of physical design implications on packet architecture (e.g., timing, area, power). Strong analytical and problem-solving abilities, with meticulous attention to detail in troubleshooting and debugging complex networking issues. Exceptional written and verbal communication skills, including the ability to document and present complex architectural concepts clearly. Why Join Us? At Eridu AI, you’ll have the opportunity to shape the future of AI infrastructure, working with a world-class team on groundbreaking technology that pushes the boundaries of AI performance. Your contributions will directly impact the next generation of AI networking solutions, transforming data center capabilities. The starting base salary for the selected candidate will be established based on their relevant skills, experience, qualifications, work location, market trends, and the compensation of employees in comparable roles. Seniority level Seniority level Mid-Senior level Employment type Employment type Full-time Job function Industries Semiconductor Manufacturing, Computer and Network Security, and Computer Hardware Manufacturing Referrals increase your chances of interviewing at Eridu AI by 2x Inferred from the description for this job Medical insurance Vision insurance 401(k) Get notified when a new job is posted. Sign in to set job alerts for “Architect” roles. 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